EN160 Design and Implementation of VLSI Systems

TextBooks

Required

Recommended

 

HWs

HW/Lab

Post Date
Due Date (solutions handout)

Graded HW handout

HW1 (ex 1.6, 1.8, 1.12, 1.16, 1.18)
Jan 31
Feb 7
Feb 12
Feb 9
Feb 16
Feb 23
Feb 23
March 2
March 7
March 9
March 16
March 21
HW5 (ex 7.2, 7.4, 7.6, 7.10)
April 4
April 11
April 22
April 22
May 7
May 7

 

Topics

ABET form

Lectures

Date
Topic PPT Notes
Wed 1/24
Introduction
Fri 1/26
CMOS logic lecture02
Mon 1/29
CMOS fabrication lecture03
Wed 1/31
CMOS layout lecture04 First HW out
Fri 2/2
Operation of MOS transistor (ideal) lecture05
Mon 2/5
Inverter DC transfer characteristics lecture06
Wed 2/7
Nonideal operation of MOS transistor lecture07 First HW due
Fri 2/9
Circuit simulation using SPICE lecture08 Second HW out
Mon 2/12
Design Layout using L-Edit lecture09
Wed 2/14
Delay Estimation lecture10  
Fri 2/16
Logical Effort (1/2) lecture11 Second HW Due.
Mon 2/19
President Day holiday  
Wed 2/21
Logical Effort (2/2) lecture12
Fri 2/23
Power dissipation lecture13 Third HW out
Mon 2/26
Interconnects lecture14  
Wed 2/28
Wire Engineering lecture15  
Fri 3/2
Scaling theory lecture16 Third HW due
Mon 3/5
Static CMOS combinational design (1/2) lecture17
Wed 3/7
Static CMOS combinational design (2/2) lecture18
Fri 3/9
Dynamic CMOS combinational design lecture19 Fourth HW out
Mon 3/12
Circuit Design Pitfalls lecture20
Wed 3/14
Differential/Sense amplifier circuits lecture21
Fri 3/16
Material Review lecture22 Fourth HW due
Mon 3/19
Sequencing circuits (1/3) lecture23
Wed 3/21
Midterm
Fri 3/23
Office hours instead
Spring Break
Mon 4/2
Sequencing circuits (2/3) lecture24
Wed 4/4
Sequencing circuits (3/3) lecture25 Fifth HW out
Fri 4/6
Project Overview lecture26
Mon 4/9
Datapath systems (1/3) lecture27
Wed 4/11
Class canceled    
Fri 4/13
Datapath systems (2/3) lecture28 Fifth HW due
Mon 4/16
Datapath systems (3/3) lecture29
Wed 4/18
Design methods (using Tanner Tools) lecture30  
Fri 4/20
Array Subsystems (1/3): SRAM lecture31  
Mon 4/23
Array Subsystems (2/3): DRAM/ROM lecture32  
Wed 4/25
Arrays Subsystems (3/3): PLDs/FPGAs lecture33
Fri 4/27
Design Methods (beyond Tanner Tools)
lecture34
Reading Period
Mon 5/7
Project Presentations
lecture35
6th HW due
Thur 5 /17
Final Exam @ 9AM B & H 165    

Project

The objective of the class project is to develop a protoype for an 8-bit subset of the MIPS processor in 0.5micron AMI process. Please see Lecture26 and Chapter 1 in your book for more details about the design of the processor. The entire class will collaborate on the design process, where each team takes a module of the processor and prototype it. An intergator will "stitch" the modules together to form the processor. The project proceeds in four phases:

Phase I (4-11 April). Standard Cell Library Design. Please make sure to functionally verify your cell design and include area/timing/power numbers in your report.

Assignee Cell
Brendan AOI22
Brian NOR2 / NOR3
Candice D Latch/FF
Jon NAND2 / NAND3
Luis Tri-State buffer
Mike Integration and verification
Nuno Xor
Sherief Inverter and Mux
Yiwen AOI21

Phase II (11-18 April). Module Specification. You are required to study your part of the CPU and make sure you write down the input-output interface of your module as well as its specification.

Team Module
Brendan - Candice FSM controller
Nuno-Yiwen ALU
Mike ALU control
Luis Register file
Brian Integration

Phase III (18-27 April). Module Prototyping. It is time to start designing and protoyping your module. In your report, make sure to include your (a) prototype layout, (b) functional (c) timing/area/power numbers. Make sure to provide clear description of how did you try to optimize / constrain your design in terms of area, time, power, and reliability.

Phase IV ( 28 April - 7 May) CPU Integration. Integration and presentation preparation. Brian have full authority to revise with you your design until it is 100% correct. He also has to piece together all the pieces to produce a functional IC prototype. He will report estimates of (1) the area (1) the speed, and (2) the power consumption of the processor.

Total Area: 1.73 mm2. #Cells = 1346
Total Wirelength = 57.6 cm
Clock Frequency = 15MHz
Power Consumption = 10.8mA

 

SPICE and L-Edit related material

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