EN164 - Spring '11: Design of Computing Systems
- Instructor: Prof. Sherief Reda (SCALE lab)
- Meeting Times: MWF 1:00 pm to 1:50 pm at B & H 158
- Office Hours: Mon and Tu 3:00 pm to 4:00 pm at BH 349 or BH 196 depending on the week.
- HW1. Due Date Fri Feb 4th
- HW2. Due Date Fri Feb 25th
- HW3. Due Date Fri Mar 11th
- HW4. Not due.
- HW5. Due Date Fri April 15th.
- HW6. Due Date Fri May 6th.
You will be using the following tools in the class labs
- MARS simulator for the MIPS architecture
- Important Note: To make programming easier, click Settings -> Memory Configuration, and choose the "Compact, Data at address 0" model.
- A summary of the MIPS instruction set is available to download.
- An assembly to verilog translator script (only instrution subset for labs) by Justin Kim.
- Altera's DE2 board fitted with a Cyclone II EP2C35 FPGA.
- Lab01. Please follow this tutorial before working on the lab. Due date Friday Feb 11.
- Lab02. Due date Friday Feb 18.
- Lab03. Due date Friday Feb 25 and Friday March 4th.
- Lab04. Due date Friday March 25 with updates on 11 and 18 of March.
- Lab05. Due date Friday April 29 with updates on 15 and 22 of April.