EN164 - Spring '12: Design of Computing Systems
- Instructor: Prof. Sherief Reda (SCALE lab)
- Meeting Times: TuTh 10:30 am to 11:50 am at B & H 165.
- Office Hours: Mon 3:00 pm to 4:00 pm and Th 2:00 pm to 3:00 pm at BH 349.
- TAs: Abdullah Nowroz and Kumud Nepal. Lab hours: 3:00 pm to 4:30 pm every week day.
Syllabus and class logistics
- Introduction (1/26, 1/31, 2/2)
- Lab Foundations (2/7, 2/14, 2/16)
- Instruction Set Architecture Design (2/23, 2/28, 3/1)
- Single-Cycle Processor Design (3/1, 3/6)
- Pipeline Processor Design (3/8, 3/13, 3/20, 3/22)
- VLIW and superscalar Processor Design (4/3, 4/5, 4/10)
- Memory Subsystem Design (4/12, 4/17, 4/19, 4/24, 4/26)
- I/O Subsystem (5/1)
- Multi-core processors and multi processors (5/3)
- HW1. Due Date Tuesday Feb 7th.
- HW2. Due Date Tuesday March 13th.
- HW3. Due Date Tuesday April 10th.
- HW4. Due Date Tuesday April 17th.
- HW5. Due Date Tuesday May 1st.
- HW6. Not due.
- Lab01. Please follow this tutorial before working on the lab. Due date Friday Feb 11.
- Lab02. Problem 5 due on Friday March 2nd. Problems 1, 2, 3, and 4 are due on Tue March 6th.
- Lab03 Due date Friday March 23rd with milestone on Friday March 16th.
- Lab04 Due date Friday April 27th with milestone on Friday April 20th.
You will be using the following tools in the class labs
- MARS simulator for the MIPS architecture
- Important Note: To make programming easier, click Settings -> Memory Configuration, and choose the "Compact, Data at address 0" model.
- A summary of the MIPS instruction set is available to download.
- Altera's DE2 board fitted with a Cyclone II EP2C35 FPGA.