|
Topic 1: Reconfigurable Logic Technology
|
 |
Topic 2: Verilog - A Hardware Definition Language
|
|
Topic 3: Design Flow
|
|
Topic 4: System-Level Synthesis
- Tu Nov 10: From Simulink to HDL
(Guest speakers: G. Venkataramani and K. Kintali from Mathworks)
- Th Nov 12: Direct Synthesis from C to HDL + P05
- Tu Nov 17: No Lecture
|
|
Topic 5: Reconfigurable Computing Architectures
- Th Nov 19: Raw Machines + P06
- Tu Nov 24: Project Progress Presentations
- Tu Dec 1:
- Th Dec 3:
|
|
Final Project Presentations
|