Lectures

Useful links

EN2911X - Fall '12: Reconfigurable Computing

  • Instructor: Prof. Sherief Reda
  • Scalable Computing Systems Laboratory
  • Meeting Times: TuTh 2:30 pm to 3:50 pm at B & H 155.
  • Office/Lab Hours: MWF (3-4 pm) and TuTh (4-5 pm)
    - Prof. Reda hours (Mon 3-4 and Th 4-5) will be at B&H 349 or lab @ B&H 196 depending on the day.
    - TA Nowroz hours TuTh 4-5 pm and W-F 3-4 pm will be @ lab B&H 196.

Lectures

You can access the videos of the lectures at Brown Streaming Server. You need to use your Brown username/password to access them.
  1. Introduction to Reconfigurable Computing (Sept 06)
  2. Programmable Logic (Sept 11, Sept 13, Sept 18)
    1. P01: The Effect of LUT and Cluster Size on Deep-Submicron FGPA Performance and Density (Sept 13)
    2. P02: The Stratix II Logic and Routing Architecture (Sept 18)
  3. Hardware Definition Languages -- Verilog (Sept 20, Sept 25, Oct 2)
  4. Reconfigurable Computing Design Methodologies (Oct 4, Oct 9, Oct 11, Oct 16, Oct 18, Oct 23, Oct 25, Nov 1, Nov 6)
  5. Application Acceleration Using Reconfigurable Computing (Nov 15)
  6. Heterogeneous Computing (Nov 20, Nov 27, Dec 4, Dec 6)

Paper review form

HWs / Labs :

Helpful lab resources: Links to Verilog books (need to be physically on Brown network or on VPN):

HW/LAB 1. Programmable Logic HW distributed in class. Due date Sept 25.

HW/LAB 2. Basic Verilog skills. Please make sure to follow this tutorial from Altera before you attempt any of the lab problems. Please download the lab assignment. Due date Sept 28 and Oct 5.

Helpful tips:

  • Details on programming the 7-segment display are given in page 30 of the DE2 manual.
  • Details on programming the switches and push buttons are given in page 26 of the DE2 manual.
  • Details on programming the LEDs are given in page 26 of the DE2 manual.
  • Note that we have covered in the class the synthesizable subset of Verilog for Altera's Quartus II. Verilog has more constructs and features that can be useful for simulations purposes.
  • Recommended HDL coding styles: Please check Section 6 of the Quartus II tool handbook.

HW/LAB 3. Please download the lab assignment. Due date Oct 12.

HW/LAB 4. Design methodologies (SW/HW partitioning + DFG). HW distributed in class. Due date Oct 18.

HW/LAB 5. Basic Soft Processing Skills using Nios II processor. Please make sure to go through this tutorial from Altera on creating and programming the Nios II system. Then please download the lab assignment.

HW/LAB 6. Application acceleration. Please download the lab assignment.