Acknowledgment of funding sources:

Publications

2018
IGSC M. Said, S. Chetoui, A. Belouchrani and S. Reda, "Understanding the sources of power consumption in Mobile SoCs," to appear in IEEE International Green and Sustainable Computing Conference, 2018.
IGSC R. Azimi, C. Jing and S. Reda, ``PowerCoord: A Coordinated Power Capping Controller for Multi-CPU/GPU Servers," to appear in IEEE International Green and Sustainable Computing Conference, 2018. Best Paper Award
ICRC C. Arcadia, H. Tann, A. Dombroski, K. Ferguson, S. L. Chen, E. Kim, B. Rubenstein, C. Rose, S. Reda and J. Rosenstein, "Parallelized Linear Classification with Volumetric Chemical Perceptrons," to appear in IEEE Conference on Rebooting Computer, 2018.
TOMPECS R. Azimi, T. Fox, W. Gonzalez and S. Reda, ``Scale-out vs Scale-up: A Study of ARM-based SoCs on Server-class workloads," to appear in ACM Transactions on Modeling and Performance Evaluation of Computing Systems, 2018.
ISIT C. Rose, S. Reda, B. Rubenstein and J. Rosenstein, ``Computing With Chemicals: Perceptrons Using Mixtures of Small Molecules", to appear in IEEE International Symposium on Information Theory, 2018.
DAC S. Hashemi, H. Tann and S. Reda, "BLASYS: Approximate Logic Circuit Synthesis Using Boolean Matrix Factorization," to appear in IEEE/ACM Design Automation Conference, 2018.
arxiv H. Tann, S. Hashemi and S. Reda, "Flexible Deep Neural Network Processing," arXiv Technical Report 1801.07353, 2018.
DATE S. Hashemi, H. Tann, F. Buttafuoco and S. Reda, "Approximate Computing for Biometric Security Systems: A Case Study on Iris Scanning," in IEEE Design, Automation Test in Europe, 2018.
DATE M. Nabavi Nejad, X. Zhan, R. Azimi, M Goudarzi, and S. Reda, "QoR-Aware Power Capping for Approximate Big Data Processing," in IEEE Design, Automation Test in Europe, 2018.
Sensors S. Reda, K. Dev and A. Belouchrani, "Blind Identification of Thermal Models and Power Sources from Thermal Measurements ," in IEEE Journal on Sensors, 2018.

2017
JOLPE K. Dev, X. Zhan and S. Reda, "Scheduling on CPU+GPU Processors under Dynamic Conditions," to appear in Journal on Low-Power Electronics (JOLPE), American Scientific Publishers, 2017.
ICCD S. Steffl and S. Reda, "LACore: A Supercomputing-Like Linear Algebra Accelerator for SoC-Based Designs," to appear in IEEE Conference on Computer Design, 2017.
Nature S. Reda, "3D Integration Advances Computing," Nature, Vol. 457, pp. 38-40, 2017. (invited article in News & Views Section).
Cluster R. Azimi, T. Fox and S. Reda, "Understanding the Role of GPGPU-accelerated SoC-based ARM Clusters," in IEEE Cluster 2017.
MSE M. Shalan and S. Reda, "CloudV: A Cloud-Based Educational Digital Design Environment," IEEE International Conference on Microelectronic Systems Education (MSE), pp. 39- 42, 2017.
iTherm F. Kaplan, S. Reda and A. Coskun, "Fast Thermal Modeling of Liquid, Thermoelectric, and Hybrid Cooling ", to appear in IEEE The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems , 2017.
DAC H. Tann, S. Hashemi, R. I. Bahar and S. Reda, "Hardware-Software Codesign of Highly Accurate, Multiplier-free Deep Neural Networks", to appear in IEEE/ACM Design Automation Conference, 2017.
DATE S. Reda and A. Belouchrani, "Blind Identification of Power Sources in Processors", to appear in IEEE/ACM Design, Automation & Test in Europe, 2017.
DATE S. Hashemi, N. Anthony, H. Tann, R. I. Bahar and S. Reda, "Understanding the Impact of Precision Quantization on the Accuracy and Energy of Neural Networks", to appear in IEEE/ACM Design, Automation and Test in Europe , 2017.
HPCA R. Azimi, M. Badiei, L. Na and S. Reda, "Fast Decentralized Power Capping for Server Clusters", to appear in IEEE Symposium on High-Performance Computer Architecture, 2017.

2016
ESTI K. Dev and S. Reda, "Scheduling Challenges and Opportunities in Integrated CPU+GPU Processors", in ACM/IEEE Symposium on Emedded Systems for Real-time Media, pp. 78-83, 2016.
IISWC K. Dev, X. Zhan and S. Reda, "Power-Aware Characterization and Mapping of Workloads on CPU-GPU Processors ", to appear in IEEE International Symposium on Workload Characterization, 2016.
TETC K. Nepal, S. Hashemi, C. Tann, R. I. Bahar and S. Reda, "Automated High-Level Generation of Low-Power Approximate Computing Circuits", to appear in IEEE Transactions on Emerging Topics in Computing, 2016.
CODES C. Tann, S. Hashemi, R. I. Bahar and S. Reda, "Runtime Configurable Deep Neural Networks for Energy-Accuracy Trade-off", to appear in IEEE International Conference on Hardware/Software Codesign and System Synthesis, 2016.
FPL O. Ulusel, C. Picardo, C. Harris, S. Reda and R. I. Bahar, "Hardware Acceleration of Feature Detection and Description Algorithms on Low-Power Embedded Platforms", to appear in IEEE Field Programmable Logic, 2016.
ISVLSI K. Dev, S. Reda, I. Paul, W. Huang and W. Burleson, "Workload-aware Power Gating Design and Run-time Management for Massively Parallel GPGPUs", to appear in IEEE Symposium on Very-Large Scale Integration, 2016.
CAL X. Zhan, R. Azimi, S. Kanev, D. Brooks and S. Reda, "CARB: A C-State Power Management Arbiter For Latency-Critical Workloads", in IEEE Computer Architecture Letters, 2016.
DAC S. Hashemi, R. I. Bahar and S. Reda, "A Low-Power Dynamic Divider for Approximate Applications", to appear in IEEE/ACM Design Automation Conference, Artile No. 105, 2016.
CCGrid X. Zin, M. Shoaib and S. Reda, "Creating Soft Heterogeneity in Clusters Through Firmware Re-configuration", in IEEE Cluster, Cloud and Grid Computing, pp. 540-549, 2016.
CCGrid M. Badiei, X. Zhan, R. Azimi, S. Reda and N. Li, "DiBA: Distributed Power Budget Allocation for Large-Scale Computing Clusters", in IEEE Cluster, Cloud and Grid Computing, pp. 70-79, 2016.

2015
IISWC R. Azimi, X. Zhan and S. Reda, "How Good Are Low-Power 64-bit SoCs for Server-Class Workloads?," in IEEE International Symposium on Workload Characterization, pp. 116-117, 2015.
ICCAD S. Hashemi, R. I. Bahar and S. Reda, "DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications," in ACM/IEEE International Conference on Computer-Aided Design, pp. 418-425, 2015. Best Paper Candidate.
ISLPED S. Jayakumar, S. Reda, "Making Sense of Thermoelectrics for Processor Thermal Management and Energy Harvesting," in ACM/IEEE International Symposium on Low-Power Electronics and Design, pp. 31-36, 2015.
TComp X. Zhan and S. Reda, "Power Budgeting Techniques for Datacenters," in IEEE Transactions on Computers, Vol. 64(8), pp. 2267-2278, 2015.

2014
TCAD A. N. Nowroz, K. Hu, F. Koushanfar, S. Reda, "Novel Techniques for High-Sensitivity Hardware Trojan Detection using Thermal and Power Maps," IEEE Transactions on Computer-Aided Design, 33(12), pp. 1792-1805, 2014.
ISLPED R. Azimi, X. Zhan and S. Reda, "Thermal-Aware Layout Planning for Heterogeneous Datacenters," in IEEE International Symposium on Low-Power Electronics and Design, 2014.
TRETS O. Ulusel, K. Nepal, R. I. Bahar and S. Reda, "Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators," in ACM Transactions on Reconfigurable Technology and Systems, 7(1), Article 4, 2014
DATE K. Nepal, Y. Li, R. I. Bahar and S. Reda, " ABACUS: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits" in Design, Automation and Test in Europe, 2014.

2013
ISLPED K. Dev, A. N. Nowroz and S. Reda, "Power Mapping and Modeling of Multi-core Processors," in IEEE International Symposium on Low-Power Electronics and Design, pp. 39-44, 2013.
ISLPED C. Hankendi S. Reda, A. Coskun, "vCap: Adaptive Power Capping for Virtualized Servers," in IEEE International Symposium on Low-Power Electronics and Design, pp. 415-420, 2013.
DAC X. Zhan and S. Reda, "Techniques for Energy-Efficient Power Budgeting in Data Centers," in Design Automation Conference, 2013.
DAC K. Dev, G. Woods and S. Reda, "High-Throughput TSV Testing and Characterization for 3D Integration Using Thermal Mapping," in Design Automation Conference, 2013.
DATE F. Paterna and S. Reda, "Mitigating Dark Silicon Problems Using Superlattice-based Thermoelectric Coolers," in Design, Automation and Test in Europe, 2013.
DATE K. Hu, A. Nowroz, S. Reda and F. Koushanfar, "High-Sensitivity Hardware Trojan Detection Using Multimodal Characterization Power Mapping of Integrated Circuits Using AC-based Thermography," in Design, Automation and Test in Europe, 2013.
TVLSI A. N. Nowroz, G. Woods and S. Reda, "Power Mapping of Integrated Circuits Using AC-based Thermography," IEEE Transactions on VLSI , Vol 21(8), pp. 1398-1409, 2013.
INTEG S. Reda, A. N. Nowroz, R. Cochran, S. Angelevski, "Post-Silicon Power Mapping Techniques for Integrated Circuits," in ElSevier VLSI\ Integration Journal,Vol 46(1), pp. 69-79, 2013.

2012
TODAES R. Cochran and S. Reda, " Thermal Prediction and Adaptive Control Through Workload Phase Detection," in ACM Transactions on Design Automation of Eletronic Systems, Vol 18(1), 7:1-7:19, 2012.
MICRO J S. Reda, R. Cochran, and A. Coskun, "Adaptive Power Capping for Servers with Multi-­threaded Workloads," IEEE Micro Journal, Vol 32(5), pp. 64-75, 2012.
FnTrends S. Reda and A. N. Nowroz, "Power Modeling and Characterization of Computing Devices: A Survey," in Foundations and Trends in Electronic Design Automation Journal, VOl. 6(2), pp. 121 - 216, 2012.
FCCM K. Nepal, O. Ulusul, R. I. Bahar and S. Reda, "Fast Multi-Objective Algorithmic-Design Co-Exploration for FPGA-based Accelerators," in IEEE International Symposium on Field-Programmable Custom Computing Machines, , pp. 65-68, 2012.

2011
MICRO R. Cochran, C. Hankendi, A. Coskun and S. Reda, "Pack & Cap: Adaptive DVFS and Thread Packing Under Power Caps," in ACM/IEEE International Symposium on Microarchitecture, pp. 175-185, 2011.
ICCAD R. Cochran, C. Hankendi, A. Coskun and S. Reda, "Identifying the Optimal Energy-Efficient Operating Points of Parallel Workloads," ACM/IEEE International Conference on Computer-Aided Design, pp. 608-615, 2011.
JETCAS S. Reda, "Thermal and Power Characterization of Real Computing Devices," IEEE Journal on Emerging Topics in Circuits and Systems, Vol. 1(2), pp. 76 - 87, 2011.
DAC A. N. Nowroz, G. Woods and S. Reda, "Improved Post-Silicon power Modeling Using AC Lock-In Techniques," ACM/IEEE Design Automation Conference, pp. 101 - 106, 2011.
TComp S. Reda, R. Cochran, and A. N. Nowroz, "Improved Thermal Tracking for Processors Using Hard and Soft Sensor Allocation Techniques," IEEE Transactions on Computers, Vol. 60(6), pp. 841 - 861, 2011.
FPGA A. N. Nowroz and S. Reda, "Thermal and Power Characterization of Field-Programmable Gate Arrays," ACM International Symposium on Field Programmable Gate Arrays, pp. 111 - 114, 2011.

2010
3DIC N. H. Khan, S. Reda and S. Hassoun, "Early Estimation of TSV Area for Power Delivery in 3D Integrated Circuits," IEEE International 3D Systems Integration Conference, pp. 1 - 6, 2010.
ISLPED R. Cochran, A. N. Nowroz and S. Reda, "Post-Silicon Power Characterization Using Thermal Infrared Emissions," International Symposium on Low-Power Electronics and Design, pp. 331-336, 2010. Best Paper Award.
TSM S. Reda and S. Nassif, "Accurate Spatial Estimation and Decomposition Techniques for Variability Characterization," IEEE Transactions on Semiconductor Manufacturing, pp. 345-357, 2010.
SLIP J. Qiu, S. Reda and S. Hassoun, "Fast, Accurate A Priori Routing Delay Estimation," System Level Interconnect Prediction, pp. 77 - 82, 2010.
DAC A. N. Nowroz, R. Cochran and S. Reda, "Thermal Monitoring of Real Processors: Techniques for Sensor Allocation and Full Characterization," Design Automation Conference, pp. 56 - 61, 2010.
DAC R. Cochran and S. Reda, "Consistent Runtime Thermal Prediction and Control Through Workload Phase Detection," Design Automation Conference , pp. 62 - 67, 2010.

2009
ISLPED S. Reda, A. Si and R. I. Bahar, "Reducing the Leakage and Timing Variability of 2D ICs Using 3D ICs," International Symposium on Low Power Electronics and Design , pp. 283 - 286, 2009.
SLIP S. Reda, "Using Circuit Structural Analysis Techniques for Networks in Systems Biology," System Level Interconnect Prediction (SLIP), pp. 37 - 44, 2009.
DAC R. Cochran and S. Reda, "Spectral Techniques for High-Resolution Thermal Characterization with Limited Sensor Data," Design Automation Conference (DAC), pp. 478 - 483, 2009.
GLSVLSI R. Le, S. Reda and R. I. Bahar, "High-Performance, Cost-Effective Heterogeneous 3D FPGA Architectures," Great Lakes VLSI Symposium, pp. 251 - 256, 2009.
GLSVLSI M. Kadin, S. Reda and G. Uht, "Central vs. Distributed Dynamic Thermal Management for Multi-Core Processors: Which one is better?," Great Lakes VLSI Symposium, pp. 137 - 140, 2009.
DATE S. Reda and S. Nassif, "Analyzing the Impact of Process Variations on Parametric Measurements: Novel Models and Applications," Design, Automation, Test in Europe, pp. 375 - 380, 2009.
TVLSI S. Reda, G. Smith and L. Smith, "Maximizing the Functional Yield of Wafer-to-Wafer 3D Integration," in IEEE Transactions on Very Large Scale Integration Systems, 17(9), pp. 1357 - 1362, 2009.

2008
JETC C. Ferri, S. Reda and R. I. Bahar, "Parametric Yield Management for 3D ICs: Models and Strategies for Improvement,"ACM Journal on Emerging Technologies in Computing Systems, Special Issue on 3D ICs, 4(4), pp. 19:1 - 19:22, 2008.
ICCD M. Kadin and S. Reda, "Frequency and Voltage Planning for Multi-Core Processors Under Thermal Constraints," International Conference on Computer Design, pp. 463 - 470, 2008.
ISLPED M. Kadin and S. Reda, "Frequency Planning for Multi-Core Processors Under Thermal Constraints," International Symposium on Low Power Electronics and Design, pp. 213-216, 2008.
ASPDAC B. Hargreaves, H. Hult and S. Reda, "Within-die Process Variations: How Accurately can They Be Statistically Modeled?" Proc. Asia-Pacific Design Automation Conference, 2008, pp. 524-530. Best Paper Candidate.

2007
ICCAD C. Ferri, S. Reda and R. I. Bahar, "Strategies for Improving the Parametric Yield and Profits of 3D ICs," Proc. International Conference on Computer-Aided Design, 2007, pp. 220-226.
ICCD D. Meisner and S. Reda, "Hardware Libraries: An Architecture for Economic Acceleration in Soft Multi-Core Environments," Proc. International Conference on Computer Design, 2007, pp. 189-196.
ISQED A. B. Kahng, S. Reda and P. Sharma, "On-Line Adjustable Buffering for Runtime Power Reduction," in Proc. International Symposium on Quality Electronic Design Automation, 2007, pp. 550 - 555.
BOOK A. Kahng and S. Reda and Q. Wang, "APlace: A High Quality, Large-Scale Analytical Placer," Modern Circuit Placement: Best Practices and Results, Springer, 2007, J. Cong and G-J. Nam (ed.), pp. 163 - 187.

2001-2006
BOOK A. Kahng, I. Mandoiu, S. Reda, A. Zelikovsky and X. Xu, "Computer-Aided Optimization of DNA Array Design and Manufacturing," Design Automation Methods and Tools for Microfluidics-Based Biochips, Springer, 2006, K. Chakrabarty (ed.), pp. 253 - 269.
TCAD A. B. Kahng, I. Mandoiu, S. Reda, X. Xu and A. Zelikvosky, "Computer-Aided Optimization of DNA Array Design and Manufacturing," IEEE Transactions on Computer-Aided Design, Vol. 25(2), 2006, pp. 305 - 320.
TCAD A. Kahng and S. Reda, "New and Improved BIST Diagnosis Techniques from Combinatorial Group Theory," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25(3), 2006, pp. 533 - 543.
TCAD A. Kahng and S. Reda, "Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, Vol. 25(12), pp. 2806 - 2819.
TCAD A. Kahng and S. Reda, "Wirelength Minimization for Min-Cut Placements via Placement Feedback," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25(7), 2006, pp. 1301 - 1312.
TCAD C. Alpert, A. B. Kahng, G-J. Nam, S. Reda and P. Villarubia "A Fast Hierarchical Quadratic Placement Algorithm," 2006, IEEE Transactions on Computer Aided Design, Vol. 25(4), 2006, pp. 678 - 691.
SLIP Andrew B. Kahng and S. Reda, "A Tale of Two Nets: Studies of Wirelength Progression in Physical Design," System Level Interconnect Prediction Workshop, 2006, pp. 17 - 24.
ISPD S. Reda and A. Chowdhary, "Effective Linear Programming Based Placement Methods," International Symposium on Physical Design, 2006, pp. 186 - 191.
BOOK A. Kahng and S. Reda, "Digital Layout - Placement," The CRC Handbook of EDA for IC Design, CRC Press, 2005, G. Martin and L. Lavagno (ed.), Vol. 2., pp. 5.1 - 5.23.
ICCAD A. B. Kahng and S. Reda, "Intrinsic Shortest Path Length: A New, Accurate A Priori Wirelength Estimator," Intl. Conf. on Computer Aided Design, 2005, pp. 173 - 180.
ICCAD A. B. Kahng, S. Reda and Q. Wang "Architecture and Details of a High Quality, Large-Scale Analytical Placer," Intl. Conf. on Computer Aided Design, 2005, pp. 891 - 898. Best Paper Candidate.
DAC Y. Cheon, P-H. Ho, A. Kahng, S. Reda and Q. Wang, "Power-Aware Placement," Design Automation Conference, 2005. pp. 795-800.
ISPD A. B. Kahng, S. Reda, and Q. Wang, "APlace: A General Analytic Placement Framework," International Symposium on Physical Design, 2005, pp. 233-235. Short invited - 1st place winner of the ISPD 2005 placement contest.
ISPD A. B. Kahng and S. Reda, "Evaluation of Placer Suboptimality Via Zero-Change Netlist Transformations," International Symposium on Physical Design, 2005, pp. 208-215.
ISPD C. Alpert, A. B. Kahng, G-J. Nam, S. Reda and P. Villarubia, "A Semi-Persistent Clustering Technique for VLSI Circuit Placement," International Symposium on Physical Design, 2005, pp. 200-207.
ICCD A. B. Kahng and S. Reda, "Reticle Floorplanning With Guaranteed Yield for Multi-Projects Wafers," in International Conference on Computer Design, 2004, pp. 106-110.
DAC A. B. Kahng and S. Reda, "Placement Feedback: A Concept and Method for Better Min-Cut Placements," ACM/IEEE Design Automation Conference, 2004, pp. 357-362.
ORLETTERS A. B. Kahng and S. Reda, "Match Twice and Stitch: A New TSP Tour Construction Heuristic," Operations Research Letters, 2004, 32(6). pp. 499-509. The most downloaded "hottest" article of Operations Research Letters in the 1st quarter of 2005 (cached link).
GLSVLSI A. B. Kahng, I. Markov and S. Reda, "On Legalization of Row-Based Placements," IEEE Great Lakes VLSI Symposium, 2004, pp. 214-219.
DATE A. B. Kahng, I. Markov and S. Reda, "Boosting: A Min-Cut Placement with Improved Signal Delay," Design Automation and Test in Europe, 2004, pp. 1098-1103.
ASPDAC A. B. Kahng and S. Reda, "Combinatorial Group Testing Methods for the BIST Diagnosis Problem," Asian South-Pacific Design Automation Conference 2004, pp. 113-116.
JCB A. B. Kahng, I. Mandoiu, P. Pevzner, S. Reda, and A. Zelikvosky, "Scalable Heuristics for Design of DNA Probe Arrays," Journal of Computational Biology, Volume 11(2-3), pp. 429-447, 2004.
ICCAD A. B. Kahng, I. Mandoiu, S. Reda, X. Xu and A. Zelikvosky, "Evaluation of Placement Techniques for DNA Probe Array Layout," Intl. Conf. on Computer Aided Design, 2003, pages 262-269.
ICCD A. B. Kahng, I. Mandoiu, S. Reda, X. Xu and A. Zelikvosky, "Design Flow Enhancements for DNA Arrays," Intl. Conf. on Computer Design, 2003, pages 116-123.
RECOMB A. B. Kahng, I. Mandoiu, P. Pevzner, S. Reda, and A. Zelikvosky, "Engineering a Scalable Placement Heuristic for DNA Probe Arrays,"  Intl. Conf. on Research in Computational Molecular Biology, 2003, pages 148-156.
WABI A. B. Kahng, I. I. Mandoiu, P. A. Pevzner, S. Reda, and A. A. Zelikovsky, "Border Length Minimization in DNA Array Design", In Proc. 2nd Workshop on Algorithms in Bioinformatics (WABI), 2002, pages 435-438.
ISQED S. Reda, R. Drechsler, A. Orailoglu, "On the Relation between BDDs and SAT for Equivalence Checking," International Symposium on Quality Electronic Design Automation, ISQED, 2002, pp. 394-399.
DATE S. Reda, A. Orailoglu, "Reducing Test Application Time through Test Data Mutation," Design Automation and Test In Europe, DATE, 2002, pp. 387-393, 2002. Best Paper Award.
DATE S. Reda, A. Salem, "Combinational Equivalence Checking using Boolean Satisfiability and Binary Decision Diagrams," Design Automation and Test In Europe, DATE, 2001, pp. 122-126.
ISCAS S. Reda, A. Wahba, A. Salem, D. Borionne, M. Ghonaimy, "On the Use of Don't Cares during Reachability Analysis," International Symposium on Circuits & Systems, ISCAS, 2001, pp. 121-124 Vol(5).

Patents
C. Alpert, G-J. Nam, S. Reda and P. Villarubia, "A Semi-Persistent Clustering Technique for VLSI Circuit Placement," Issued US Patent, US7296252.