2018 
IGSC 
M. Said, S. Chetoui, A. Belouchrani and S. Reda, "Understanding the sources of power consumption in Mobile SoCs," to appear in IEEE International Green and Sustainable Computing Conference, 2018. 
IGSC 
R. Azimi, C. Jing and S. Reda, ``PowerCoord: A Coordinated Power Capping Controller for MultiCPU/GPU Servers," to appear in IEEE International Green and Sustainable Computing Conference, 2018. 
ICRC 
C. Arcadia, H. Tann, A. Dombroski, K. Ferguson, S. L. Chen, E. Kim, B. Rubenstein, C. Rose, S. Reda and J. Rosenstein, "Parallelized Linear Classification with Volumetric Chemical Perceptrons," to appear in IEEE Conference on Rebooting Computer, 2018. 
TOMPECS 
R. Azimi, T. Fox, W. Gonzalez and S. Reda, ``Scaleout vs Scaleup: A Study of ARMbased SoCs on Serverclass workloads," to appear in ACM Transactions on Modeling and Performance Evaluation of Computing Systems, 2018. 
ISIT 
C. Rose, S. Reda, B. Rubenstein and J. Rosenstein, ``Computing With Chemicals: Perceptrons Using Mixtures of Small Molecules", to appear in IEEE International Symposium on Information Theory, 2018. 
DAC 
S. Hashemi, H. Tann and S. Reda, "BLASYS: Approximate Logic Circuit Synthesis Using Boolean Matrix Factorization," to appear in IEEE/ACM Design Automation Conference, 2018. 
arxiv 
H. Tann, S. Hashemi and S. Reda, "Flexible Deep Neural Network Processing," arXiv Technical Report 1801.07353, 2018. 
DATE 
S. Hashemi, H. Tann, F. Buttafuoco and S. Reda, "Approximate Computing for Biometric Security Systems: A Case Study on Iris Scanning," in IEEE Design, Automation Test in Europe, 2018. 
DATE 
M. Nabavi Nejad, X. Zhan, R. Azimi, M Goudarzi, and S. Reda, "QoRAware Power Capping for Approximate Big Data Processing," in IEEE Design, Automation Test in Europe, 2018. 
Sensors 
S. Reda, K. Dev and A. Belouchrani, "Blind Identification of Thermal Models and Power Sources from Thermal Measurements
," in IEEE Journal on Sensors, 2018. 
2017 
JOLPE 
K. Dev, X. Zhan and S. Reda, "Scheduling on CPU+GPU Processors under Dynamic Conditions," to appear in Journal on LowPower Electronics (JOLPE), American Scientific Publishers, 2017.

ICCD 
S. Steffl and S. Reda, "LACore: A SupercomputingLike Linear Algebra Accelerator for SoCBased Designs," to appear in IEEE Conference on Computer Design, 2017.

Nature 
S. Reda, "3D Integration Advances Computing," Nature, Vol. 457, pp. 3840, 2017. (invited article in News & Views Section).

Cluster 
R. Azimi, T. Fox and S. Reda, "Understanding the Role of GPGPUaccelerated SoCbased ARM Clusters," in IEEE Cluster 2017.

MSE 
M. Shalan and S. Reda, "CloudV: A CloudBased Educational Digital Design Environment," IEEE International Conference on Microelectronic Systems Education (MSE), pp. 39 42, 2017.

iTherm 
F. Kaplan, S. Reda and A. Coskun, "Fast Thermal Modeling of Liquid, Thermoelectric, and Hybrid Cooling
", to appear in IEEE The Intersociety Conference on Thermal and
Thermomechanical Phenomena in Electronic Systems
, 2017.

DAC 
H. Tann, S. Hashemi, R. I. Bahar and S. Reda, "HardwareSoftware Codesign of Highly
Accurate, Multiplierfree Deep Neural Networks", to appear in IEEE/ACM Design Automation Conference, 2017.

DATE 
S. Reda and A. Belouchrani, "Blind Identification of Power Sources in
Processors", to appear in IEEE/ACM Design, Automation & Test in Europe, 2017.

DATE 
S. Hashemi, N. Anthony, H. Tann, R. I. Bahar and S. Reda, "Understanding the Impact of Precision Quantization
on the Accuracy and Energy of Neural Networks", to appear in IEEE/ACM Design, Automation and Test in Europe , 2017.

HPCA 
R. Azimi, M. Badiei, L. Na and S. Reda, "Fast Decentralized Power Capping for Server Clusters", to appear in IEEE Symposium on HighPerformance Computer Architecture, 2017.

2016 
ESTI 
K. Dev and S. Reda, "Scheduling Challenges and Opportunities in Integrated CPU+GPU Processors", in ACM/IEEE Symposium on Emedded Systems for Realtime Media, pp. 7883, 2016.

IISWC 
K. Dev, X. Zhan and S. Reda, "PowerAware Characterization and Mapping of
Workloads on CPUGPU Processors
", to appear in IEEE International Symposium on Workload Characterization, 2016.

TETC 
K. Nepal, S. Hashemi, C. Tann, R. I. Bahar and S. Reda, "Automated HighLevel Generation of LowPower Approximate Computing Circuits", to appear in IEEE Transactions on Emerging Topics in Computing, 2016. 
CODES 
C. Tann, S. Hashemi, R. I. Bahar and S. Reda, "Runtime Configurable Deep Neural Networks for EnergyAccuracy Tradeoff", to appear in IEEE International Conference on Hardware/Software Codesign and System Synthesis, 2016.

FPL 
O. Ulusel, C. Picardo, C. Harris, S. Reda and R. I. Bahar, "Hardware Acceleration of Feature Detection and Description Algorithms on LowPower Embedded Platforms", to appear in IEEE Field Programmable Logic, 2016.

ISVLSI 
K. Dev, S. Reda, I. Paul, W. Huang and W. Burleson, "Workloadaware Power Gating Design and Runtime Management for Massively Parallel GPGPUs", to appear in IEEE Symposium on VeryLarge Scale Integration, 2016.

CAL 
X. Zhan, R. Azimi, S. Kanev, D. Brooks and S. Reda, "CARB: A CState Power Management Arbiter For LatencyCritical Workloads", in IEEE Computer Architecture Letters, 2016.

DAC 
S. Hashemi, R. I. Bahar and S. Reda, "A LowPower Dynamic Divider for Approximate Applications", to appear in IEEE/ACM Design Automation Conference, Artile No. 105, 2016. 
CCGrid 
X. Zin, M. Shoaib and S. Reda, "Creating Soft Heterogeneity in Clusters Through Firmware Reconfiguration", in IEEE Cluster, Cloud and Grid Computing, pp. 540549, 2016.

CCGrid 
M. Badiei, X. Zhan, R. Azimi, S. Reda and N. Li, "DiBA: Distributed Power Budget Allocation for LargeScale Computing Clusters", in IEEE Cluster, Cloud and Grid Computing, pp. 7079, 2016.

2015 
IISWC 
R. Azimi, X. Zhan and S. Reda, "How Good Are LowPower 64bit SoCs for ServerClass Workloads?," in IEEE International Symposium on Workload Characterization, pp. 116117, 2015.

ICCAD 
S. Hashemi, R. I. Bahar and S. Reda, "DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications," in ACM/IEEE International Conference on ComputerAided Design, pp. 418425, 2015. Best Paper Candidate. 
ISLPED 
S. Jayakumar, S. Reda, "Making Sense of Thermoelectrics for Processor Thermal Management and Energy Harvesting," in ACM/IEEE International Symposium on LowPower Electronics and Design, pp. 3136, 2015.

TComp 
X. Zhan and S. Reda, "Power Budgeting Techniques for Datacenters," in IEEE Transactions on Computers, Vol. 64(8), pp. 22672278, 2015.

2014 
TCAD 
A. N. Nowroz, K. Hu, F. Koushanfar, S. Reda, "Novel Techniques for HighSensitivity Hardware Trojan Detection using Thermal and Power Maps," IEEE Transactions on ComputerAided Design, 33(12), pp. 17921805, 2014.

ISLPED 
R. Azimi, X. Zhan and S. Reda, "ThermalAware Layout Planning for Heterogeneous Datacenters," in IEEE International Symposium on LowPower Electronics and Design, 2014.

TRETS 
O. Ulusel, K. Nepal, R. I. Bahar and S. Reda, "Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGABased Accelerators," in ACM Transactions on Reconfigurable Technology and Systems, 7(1), Article 4, 2014 
DATE 
K. Nepal, Y. Li, R. I. Bahar and S. Reda, "
ABACUS: A Technique for Automated Behavioral Synthesis
of Approximate Computing Circuits" in Design, Automation and Test in Europe, 2014. 
2013 
ISLPED 
K. Dev, A. N. Nowroz and S. Reda, "Power Mapping and Modeling of Multicore Processors," in IEEE International Symposium on LowPower Electronics and Design, pp. 3944, 2013. 
ISLPED 
C. Hankendi S. Reda, A. Coskun, "vCap: Adaptive Power Capping for Virtualized Servers," in IEEE International Symposium on LowPower Electronics and Design, pp. 415420, 2013. 
DAC 
X. Zhan and S. Reda, "Techniques for EnergyEfficient Power Budgeting in Data Centers," in Design Automation Conference, 2013. 
DAC 
K. Dev, G. Woods and S. Reda, "HighThroughput TSV Testing and Characterization for 3D Integration Using Thermal Mapping," in Design Automation Conference, 2013. 
DATE 
F. Paterna and S. Reda, "Mitigating Dark Silicon Problems Using Superlatticebased Thermoelectric Coolers," in Design, Automation and Test in Europe, 2013. 
DATE 
K. Hu, A. Nowroz, S. Reda and F. Koushanfar, "HighSensitivity Hardware Trojan Detection Using Multimodal Characterization Power Mapping of Integrated Circuits Using ACbased Thermography," in Design, Automation and Test in Europe, 2013. 
TVLSI 
A. N. Nowroz, G. Woods and S. Reda, "Power Mapping of Integrated Circuits Using ACbased Thermography," IEEE Transactions on VLSI
, Vol 21(8), pp. 13981409, 2013. 
INTEG 
S. Reda, A. N. Nowroz, R. Cochran, S. Angelevski, "PostSilicon Power Mapping Techniques for Integrated Circuits," in ElSevier VLSI\ Integration Journal,Vol 46(1), pp. 6979, 2013. 
2012 
TODAES 
R. Cochran and S. Reda, " Thermal Prediction and Adaptive Control Through Workload Phase Detection," in ACM Transactions on Design Automation of Eletronic Systems, Vol 18(1), 7:17:19, 2012. 
MICRO J 
S. Reda, R. Cochran, and A. Coskun, "Adaptive Power Capping for Servers with Multithreaded Workloads," IEEE Micro Journal, Vol 32(5), pp. 6475, 2012. 
FnTrends 
S. Reda and A. N. Nowroz, "Power Modeling and Characterization of Computing Devices: A Survey," in Foundations and Trends in Electronic Design Automation Journal, VOl. 6(2), pp. 121  216, 2012. 
FCCM 
K. Nepal, O. Ulusul, R. I. Bahar and S. Reda, "Fast MultiObjective AlgorithmicDesign CoExploration for FPGAbased Accelerators," in IEEE International Symposium on FieldProgrammable Custom Computing Machines, , pp. 6568, 2012. 
2011 
MICRO 
R. Cochran, C. Hankendi, A. Coskun and S. Reda, "Pack & Cap: Adaptive DVFS and Thread Packing Under Power Caps," in ACM/IEEE International Symposium on Microarchitecture, pp. 175185, 2011. 
ICCAD 
R. Cochran, C. Hankendi, A. Coskun and S. Reda, "Identifying the Optimal EnergyEfﬁcient Operating Points of Parallel Workloads," ACM/IEEE International Conference on ComputerAided Design, pp. 608615, 2011. 
JETCAS 
S. Reda, "Thermal and Power Characterization of Real Computing Devices," IEEE Journal on Emerging Topics in Circuits and Systems, Vol. 1(2), pp. 76  87, 2011. 
DAC 
A. N. Nowroz, G. Woods and S. Reda, "Improved PostSilicon power Modeling Using AC LockIn Techniques," ACM/IEEE Design Automation Conference, pp. 101  106, 2011. 
TComp 
S. Reda, R. Cochran, and A. N. Nowroz, "Improved Thermal Tracking for Processors Using Hard and Soft Sensor Allocation Techniques," IEEE Transactions on Computers, Vol. 60(6), pp. 841  861, 2011. 
FPGA 
A. N. Nowroz and S. Reda, "Thermal and Power Characterization of FieldProgrammable Gate Arrays," ACM International Symposium on Field Programmable Gate Arrays, pp. 111  114, 2011. 
2010 
3DIC 
N. H. Khan, S. Reda and S. Hassoun, "Early Estimation of TSV Area for Power Delivery in 3D Integrated Circuits," IEEE International 3D Systems Integration Conference, pp. 1  6, 2010. 
ISLPED 
R. Cochran, A. N. Nowroz and S. Reda, "PostSilicon Power Characterization Using Thermal Infrared Emissions," International Symposium on LowPower Electronics and Design, pp. 331336, 2010. Best Paper Award. 
TSM 
S. Reda and S. Nassif, "Accurate Spatial Estimation and Decomposition Techniques for Variability Characterization," IEEE Transactions on Semiconductor Manufacturing, pp. 345357, 2010. 
SLIP 
J. Qiu, S. Reda and S. Hassoun, "Fast, Accurate A Priori Routing Delay Estimation," System Level Interconnect Prediction, pp. 77  82, 2010. 
DAC 
A. N. Nowroz, R. Cochran and S. Reda, "Thermal Monitoring of Real Processors: Techniques for Sensor Allocation and Full Characterization," Design Automation Conference, pp. 56  61, 2010. 
DAC 
R. Cochran and S. Reda, "Consistent Runtime Thermal Prediction and Control Through Workload Phase Detection," Design Automation Conference , pp. 62  67, 2010. 
2009 
ISLPED 
S. Reda, A. Si and R. I. Bahar, "Reducing the Leakage and Timing Variability of 2D ICs Using 3D ICs," International Symposium on Low Power Electronics and Design , pp. 283  286, 2009. 
SLIP 
S. Reda, "Using Circuit Structural Analysis Techniques for Networks in Systems Biology," System Level Interconnect Prediction (SLIP), pp. 37  44, 2009. 
DAC 
R. Cochran and S. Reda, "Spectral Techniques for HighResolution Thermal Characterization with Limited Sensor Data," Design Automation Conference (DAC), pp. 478  483, 2009. 
GLSVLSI 
R. Le, S. Reda and R. I. Bahar, "HighPerformance, CostEffective Heterogeneous 3D FPGA Architectures," Great Lakes VLSI Symposium, pp. 251  256, 2009. 
GLSVLSI 
M. Kadin, S. Reda and G. Uht, "Central vs. Distributed Dynamic Thermal Management for MultiCore Processors: Which one is better?," Great Lakes VLSI Symposium, pp. 137  140, 2009. 
DATE 
S. Reda and S. Nassif, "Analyzing the Impact of Process Variations on Parametric Measurements: Novel Models and Applications," Design, Automation, Test in Europe, pp. 375  380, 2009. 
TVLSI 
S. Reda, G. Smith and L. Smith, "Maximizing the Functional Yield of WafertoWafer 3D Integration," in IEEE Transactions on Very Large Scale Integration Systems, 17(9), pp. 1357  1362, 2009. 
2008 
JETC 
C. Ferri, S. Reda and R. I. Bahar, "Parametric Yield Management for 3D ICs: Models and Strategies for Improvement,"ACM Journal on Emerging Technologies in Computing Systems, Special Issue on 3D ICs, 4(4), pp. 19:1  19:22, 2008. 
ICCD 
M. Kadin and S. Reda, "Frequency and Voltage Planning for MultiCore Processors Under Thermal Constraints," International Conference on Computer Design, pp. 463  470, 2008. 
ISLPED 
M. Kadin and S. Reda, "Frequency Planning for MultiCore Processors Under Thermal Constraints," International Symposium on Low Power Electronics and Design, pp. 213216, 2008. 
ASPDAC 
B. Hargreaves, H. Hult and S. Reda, "Withindie Process Variations: How Accurately can They Be Statistically Modeled?" Proc. AsiaPacific Design Automation Conference, 2008, pp. 524530. Best Paper Candidate. 
2007 
ICCAD 
C. Ferri, S. Reda and R. I. Bahar, "Strategies for Improving the Parametric Yield and Profits of 3D ICs," Proc. International Conference on ComputerAided Design, 2007, pp. 220226. 
ICCD 
D. Meisner and S. Reda, "Hardware Libraries: An Architecture for Economic Acceleration in Soft MultiCore Environments," Proc. International Conference on Computer Design, 2007, pp. 189196. 
ISQED 
A. B. Kahng, S. Reda and P. Sharma, "OnLine Adjustable Buffering for Runtime Power Reduction," in Proc. International Symposium on Quality Electronic Design Automation, 2007, pp. 550  555. 
BOOK 
A. Kahng and S. Reda and Q. Wang, "APlace: A High Quality, LargeScale Analytical Placer," Modern Circuit Placement: Best Practices and Results, Springer, 2007, J. Cong and GJ. Nam (ed.), pp. 163  187. 
20012006 
BOOK 
A. Kahng, I. Mandoiu, S. Reda, A. Zelikovsky and X. Xu, "ComputerAided Optimization of DNA Array Design and Manufacturing," Design Automation Methods and Tools for MicrofluidicsBased Biochips, Springer, 2006, K. Chakrabarty (ed.), pp. 253  269. 
TCAD 
A. B. Kahng, I. Mandoiu, S. Reda, X. Xu and A. Zelikvosky, "ComputerAided Optimization of DNA Array Design and Manufacturing," IEEE Transactions on ComputerAided Design, Vol. 25(2), 2006, pp. 305  320. 
TCAD 
A. Kahng and S. Reda, "New and Improved BIST Diagnosis Techniques from Combinatorial Group Theory," IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, Vol. 25(3), 2006, pp. 533  543. 
TCAD 
A. Kahng and S. Reda, "ZeroChange Netlist Transformations: A New Technique for Placement Benchmarking," IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, 2006, Vol. 25(12), pp. 2806  2819. 
TCAD 
A. Kahng and S. Reda, "Wirelength Minimization for MinCut Placements via Placement Feedback," IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, Vol. 25(7), 2006, pp. 1301  1312. 
TCAD 
C. Alpert, A. B. Kahng, GJ. Nam, S. Reda and P. Villarubia "A Fast Hierarchical Quadratic Placement Algorithm," 2006, IEEE Transactions on Computer Aided Design, Vol. 25(4), 2006, pp. 678  691. 
SLIP 
Andrew B. Kahng and S. Reda, "A Tale of Two Nets: Studies of Wirelength Progression in Physical Design," System Level Interconnect Prediction Workshop, 2006, pp. 17  24. 
ISPD 
S. Reda and A. Chowdhary, "Effective Linear Programming Based Placement Methods," International Symposium on Physical Design, 2006, pp. 186  191. 
BOOK 
A. Kahng and S. Reda, "Digital Layout  Placement," The CRC Handbook of EDA for IC Design, CRC Press, 2005, G. Martin and L. Lavagno (ed.), Vol. 2., pp. 5.1  5.23. 
ICCAD 
A. B. Kahng and S. Reda, "Intrinsic Shortest Path Length: A New, Accurate A Priori Wirelength Estimator," Intl. Conf. on Computer Aided Design, 2005, pp. 173  180. 
ICCAD 
A. B. Kahng, S. Reda and Q. Wang "Architecture and Details of a High Quality, LargeScale Analytical Placer," Intl. Conf. on Computer Aided Design, 2005, pp. 891  898. Best Paper Candidate. 
DAC 
Y. Cheon, PH. Ho, A. Kahng, S. Reda and Q. Wang, "PowerAware Placement," Design Automation Conference, 2005. pp. 795800. 
ISPD 
A. B. Kahng, S. Reda, and Q. Wang, "APlace: A General Analytic Placement Framework," International Symposium on Physical Design, 2005, pp. 233235. Short invited  1st place winner of the ISPD 2005 placement contest. 
ISPD 
A. B. Kahng and S. Reda, "Evaluation of Placer Suboptimality Via ZeroChange Netlist Transformations," International Symposium on Physical Design, 2005, pp. 208215. 
ISPD 
C. Alpert, A. B. Kahng, GJ. Nam, S. Reda and P. Villarubia, "A SemiPersistent Clustering Technique for VLSI Circuit Placement," International Symposium on Physical Design, 2005, pp. 200207. 
ICCD 
A. B. Kahng and S. Reda, "Reticle Floorplanning With Guaranteed Yield for MultiProjects Wafers," in International Conference on Computer Design, 2004, pp. 106110. 
DAC 
A. B. Kahng and S. Reda, "Placement Feedback: A Concept and Method for Better MinCut Placements," ACM/IEEE Design Automation Conference, 2004, pp. 357362. 
ORLETTERS 
A. B. Kahng and S. Reda, "Match Twice and Stitch: A New TSP Tour Construction Heuristic," Operations Research Letters, 2004, 32(6). pp. 499509. The most downloaded "hottest" article of Operations Research Letters in the 1st quarter of 2005 (cached link). 
GLSVLSI 
A. B. Kahng, I. Markov and S. Reda, "On Legalization of RowBased Placements," IEEE Great Lakes VLSI Symposium, 2004, pp. 214219. 
DATE 
A. B. Kahng, I. Markov and S. Reda, "Boosting: A MinCut Placement with Improved Signal Delay," Design Automation and Test in Europe, 2004, pp. 10981103. 
ASPDAC 
A. B. Kahng and S. Reda, "Combinatorial Group Testing Methods for the BIST Diagnosis Problem," Asian SouthPacific Design Automation Conference 2004, pp. 113116. 
JCB 
A. B. Kahng, I. Mandoiu, P. Pevzner, S. Reda, and A. Zelikvosky, "Scalable Heuristics for Design of DNA Probe Arrays," Journal of Computational Biology, Volume 11(23), pp. 429447, 2004. 
ICCAD 
A. B. Kahng, I. Mandoiu, S. Reda, X. Xu and A. Zelikvosky, "Evaluation of Placement Techniques for DNA Probe Array Layout," Intl. Conf. on Computer Aided Design, 2003, pages 262269. 
ICCD 
A. B. Kahng, I. Mandoiu, S. Reda, X. Xu and A. Zelikvosky, "Design Flow Enhancements for DNA Arrays," Intl. Conf. on Computer Design, 2003, pages 116123. 
RECOMB 
A. B. Kahng, I. Mandoiu, P. Pevzner, S. Reda, and A. Zelikvosky, "Engineering a Scalable Placement Heuristic for DNA Probe Arrays," Intl. Conf. on Research in Computational Molecular Biology, 2003, pages 148156. 
WABI 
A. B. Kahng, I. I. Mandoiu, P. A. Pevzner, S. Reda, and A. A. Zelikovsky, "Border Length Minimization in DNA Array Design", In Proc. 2nd Workshop on Algorithms in Bioinformatics (WABI), 2002, pages 435438. 
ISQED 
S. Reda, R. Drechsler, A. Orailoglu, "On the Relation between BDDs and SAT for Equivalence Checking," International Symposium on Quality Electronic Design Automation, ISQED, 2002, pp. 394399. 
DATE 
S. Reda, A. Orailoglu, "Reducing Test Application Time through Test Data Mutation," Design Automation and Test In Europe, DATE, 2002, pp. 387393, 2002. Best Paper Award. 
DATE 
S. Reda, A. Salem, "Combinational Equivalence Checking using Boolean Satisfiability and Binary Decision Diagrams," Design Automation and Test In Europe, DATE, 2001, pp. 122126. 
ISCAS 
S. Reda, A. Wahba, A. Salem, D. Borionne, M. Ghonaimy, "On the Use of Don't Cares during Reachability Analysis," International Symposium on Circuits & Systems, ISCAS, 2001, pp. 121124 Vol(5). 
Patents 

C. Alpert, GJ. Nam, S. Reda and P. Villarubia, "A SemiPersistent Clustering Technique for VLSI Circuit Placement," Issued US Patent, US7296252. 