Lectures

Useful links

EN2911X - Fall '14: Reconfigurable Computing

• Instructor: Prof. Sherief Reda
• Scalable Computing Systems Laboratory
• Meeting Times: MWF 12:00 pm to 12:50 pm at B & H 159.
• Office/Lab Hours: Mon (3-4 pm) & Wed (4-5 pm) @ B&H 349 or B&H 196
  - TA Marco Donato. Lab hours M: 4-5, Th: 4-5, Fri 3-5pm @ B&H 196.

Lectures

0. Introduction to Reconfigurable Computing (Sept 03, Sept 05)
1. Programmable Logic (Sept 08, Sept 10, Sept 12, Sept 15, Sept 17, Sept 19)
Reading resources (make sure you are on Brown network):
• FPGA Architecture: Survey and Challenges (Sections 1 - 5)
• Reconfigurable computing: a survey of systems and software (Sections 1-3)
• The effect of LUT and cluster size on deep-submicron FPGA performance and density
• Case study: Cyclone II FPGA device
2. Hardware Definition Languages -- Verilog (Sept 19, Sept 22, Sept 24, Sept 26, Sept 29)
Reading resources (make sure you are on Brown network):
• Introduction to Logic Synthesis using Verilog HDL
• Verilog Quickstart
• The Verilog Hardware Description Language
• Verilog HDL quick reference by R. Madhavan
3. Reconfigurable Computing Design Methodologies (all lectures in October and Nov 2)
• FPGA design automation: A survey
• Compiling for reconfigurable computing: A survey
4. Application Acceleration Using Reconfigurable Computing (Nov 12, Nov 14, Nov 19, Nov 21, Nov 20 and Nov 24)
• LegUp: High-Level Synthesis for FPGA-Based Processor/Accelerator Systems (Nov 21)
• Warp Processing: Dynamic Translation of Binaries to FPGA Circuits (Nov 21)
• High-Level Synthesis for FPGAs: From Prototyping to Deployment (Nov 24)
• Exploration and customization of FPGA-based soft processors (Nov 24)
5. Heterogeneous Computing (Dec 1, Dec 3 and Dec 5)
• Accelerating Compute-Intensive Applications with GPUs and FPGAs
• A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications

Paper review form

HWs / Labs :

1. HW 01 (Due date Friday Sept 19)
2. HW 02 (Due date Friday Sept 25) - Tutorial 1
3. HW 03 (Due date Friday Oct 3rd & Oct 10th) - Tutorial 2
4. HW 04 (Due Date Friday Oct 10th)
5. HW 05 (Due Date Friday Oct 17th)
6. HW 06 (Due Date Friday Oct 24th) -- Nios II Tutorial
7. HW 07 (Due Date Friday Oct 31st)
8. HW 08 (Due Dates Friday Nov 14 and Nov 21)
• Guide to increasing the frequency of the PLL
• Guide to creating custom instructions for Nios II
• Guide to creating components in QSys
• Guide to creating multi-core Nios II processors

• Quartus II tutorials
• Quartus II handbook
• DE2 manual
• DE2 pin assignment file (csv)
• Cyclone II datasheet
• Signal Tap tutorial
• TimingQuest tutorial

• Introduction to Logic Synthesis using Verilog HDL
• Verilog Digital System Design
• Verilog Quickstart
• The Verilog Hardware Description Language
• Verilog HDL quick reference by R. Madhavan